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mdbx: fix for MIPS cacheflush().

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This commit is contained in:
Leo Yuriev 2018-03-22 17:58:35 +03:00
parent 5ce40269b3
commit c52a57dac5
1 changed files with 8 additions and 4 deletions
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12
src/osal.h
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@ -366,19 +366,23 @@ static __inline void mdbx_memory_barrier(void) {
#define mdbx_coherent_barrier() mdbx_memory_barrier()
#endif
#if defined(__mips) && defined(__linux)
#if defined(__mips) || defined(__mips__) || defined(__mips64) || \
defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
/* Only MIPS has explicit cache control */
#include <asm/cachectl.h>
#include <sys/cachectl.h>
#endif
static __inline void mdbx_invalidate_cache(void *addr, size_t nbytes) {
mdbx_coherent_barrier();
#if defined(__mips) && defined(__linux)
#if defined(__mips) || defined(__mips__) || defined(__mips64) || \
defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
#if defined(DCACHE)
/* MIPS has cache coherency issues.
* Note: for any nbytes >= on-chip cache size, entire is flushed. */
cacheflush(addr, nbytes, DCACHE);
#elif defined(_M_MRX000) || defined(_MIPS_)
#else
#error "Sorry, cacheflush() for MIPS not implemented"
#endif /* __mips__ */
#else
/* LY: assume no relevant mmap/dcache issues. */
(void)addr;