From c52a57dac5ee0a543fc126838dadd5c59fdd2bac Mon Sep 17 00:00:00 2001
From: Leo Yuriev <leo@yuriev.ru>
Date: Thu, 22 Mar 2018 17:58:35 +0300
Subject: [PATCH] mdbx: fix for MIPS cacheflush().

---
 src/osal.h | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/osal.h b/src/osal.h
index 03a054b3..2b14fc29 100644
--- a/src/osal.h
+++ b/src/osal.h
@@ -366,19 +366,23 @@ static __inline void mdbx_memory_barrier(void) {
 #define mdbx_coherent_barrier() mdbx_memory_barrier()
 #endif
 
-#if defined(__mips) && defined(__linux)
+#if defined(__mips) || defined(__mips__) || defined(__mips64) ||               \
+    defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
 /* Only MIPS has explicit cache control */
-#include <asm/cachectl.h>
+#include <sys/cachectl.h>
 #endif
 
 static __inline void mdbx_invalidate_cache(void *addr, size_t nbytes) {
   mdbx_coherent_barrier();
-#if defined(__mips) && defined(__linux)
+#if defined(__mips) || defined(__mips__) || defined(__mips64) ||               \
+    defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
+#if defined(DCACHE)
   /* MIPS has cache coherency issues.
    * Note: for any nbytes >= on-chip cache size, entire is flushed. */
   cacheflush(addr, nbytes, DCACHE);
-#elif defined(_M_MRX000) || defined(_MIPS_)
+#else
 #error "Sorry, cacheflush() for MIPS not implemented"
+#endif /* __mips__ */
 #else
   /* LY: assume no relevant mmap/dcache issues. */
   (void)addr;