mirror of
https://github.com/isar/libmdbx.git
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140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/*****************************************************************************
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* Properly compiler/memory/coherence barriers
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* in the most portable way for ReOpenLDAP project.
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*
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* Feedback and comments are welcome.
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* https://gist.github.com/leo-yuriev/ba186a6bf5cf3a27bae7 */
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#if defined(__mips) && defined(__linux)
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/* Only MIPS has explicit cache control */
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# include <asm/cachectl.h>
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#endif
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#if defined(__GNUC__) || defined(__clang__)
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# define MDBX_INLINE __inline
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#elif defined(__INTEL_COMPILER) /* LY: Intel Compiler may mimic GCC and MSC */
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# include <intrin.h>
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# if defined(__ia64__) || defined(__ia64) || defined(_M_IA64)
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# pragma intrinsic(__mf)
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# elif defined(__i386__) || defined(__x86_64__)
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# pragma intrinsic(_mm_mfence)
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# endif
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# define MDBX_INLINE __inline
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#elif defined(__SUNPRO_C) || defined(__sun) || defined(sun)
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# include <mbarrier.h>
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# define MDBX_INLINE inline
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#elif (defined(_HPUX_SOURCE) || defined(__hpux) || defined(__HP_aCC)) \
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&& (defined(HP_IA64) || defined(__ia64))
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# include <machine/sys/inline.h>
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# define MDBX_INLINE
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#elif defined(__IBMC__) && defined(__powerpc)
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# include <atomic.h>
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# define MDBX_INLINE
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#elif defined(_AIX)
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# include <builtins.h>
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# include <sys/atomic_op.h>
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# define MDBX_INLINE
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#elif (defined(__osf__) && defined(__DECC)) || defined(__alpha)
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# include <machine/builtins.h>
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# include <c_asm.h>
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# define MDBX_INLINE
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#elif defined(__MWERKS__)
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/* CodeWarrior - troubles ? */
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# pragma gcc_extensions
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# define MDBX_INLINE
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#elif defined(__SNC__)
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/* Sony PS3 - troubles ? */
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# define MDBX_INLINE
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#else
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# define MDBX_INLINE
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#endif
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#if defined(__i386__) || defined(__x86_64__) \
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|| defined(_M_AMD64) || defined(_M_IX86) \
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|| defined(__i386) || defined(__amd64) \
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|| defined(i386) || defined(__x86_64) \
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|| defined(_AMD64_) || defined(_M_X64)
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# define MDB_CACHE_IS_COHERENT 1
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#elif defined(__hppa) || defined(__hppa__)
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# define MDB_CACHE_IS_COHERENT 1
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#endif
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#ifndef MDB_CACHE_IS_COHERENT
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# define MDB_CACHE_IS_COHERENT 0
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#endif
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#define MDBX_BARRIER_COMPILER 0
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#define MDBX_BARRIER_MEMORY 1
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static MDBX_INLINE void mdbx_barrier(int type) {
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#if defined(__clang__)
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__asm__ __volatile__ ("" ::: "memory");
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if (type > MDBX_BARRIER_COMPILER)
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# if __has_extension(c_atomic) || __has_extension(cxx_atomic)
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__c11_atomic_thread_fence(__ATOMIC_SEQ_CST);
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# else
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__sync_synchronize();
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# endif
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#elif defined(__GNUC__)
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__asm__ __volatile__ ("" ::: "memory");
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if (type > MDBX_BARRIER_COMPILER)
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# if defined(__ATOMIC_SEQ_CST)
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__atomic_thread_fence(__ATOMIC_SEQ_CST);
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# else
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__sync_synchronize();
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# endif
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#elif defined(__INTEL_COMPILER) /* LY: Intel Compiler may mimic GCC and MSC */
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__memory_barrier();
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if (type > MDBX_BARRIER_COMPILER)
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# if defined(__ia64__) || defined(__ia64) || defined(_M_IA64)
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__mf();
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# elif defined(__i386__) || defined(__x86_64__)
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_mm_mfence();
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# else
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# error "Unknown target for Intel Compiler, please report to us."
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# endif
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#elif defined(__SUNPRO_C) || defined(__sun) || defined(sun)
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__compiler_barrier();
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if (type > MDBX_BARRIER_COMPILER)
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__machine_rw_barrier();
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#elif (defined(_HPUX_SOURCE) || defined(__hpux) || defined(__HP_aCC)) \
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&& (defined(HP_IA64) || defined(__ia64))
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_Asm_sched_fence(/* LY: no-arg meaning 'all expect ALU', e.g. 0x3D3D */);
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if (type > MDBX_BARRIER_COMPILER)
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_Asm_mf();
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#elif defined(_AIX) || defined(__ppc__) || defined(__powerpc__) \
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|| defined(__ppc64__) || defined(__powerpc64__)
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__fence();
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if (type > MDBX_BARRIER_COMPILER)
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__lwsync();
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#elif (defined(__osf__) && defined(__DECC)) || defined(__alpha)
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__PAL_DRAINA(); /* LY: excessive ? */
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__MB();
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#else
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# error "Could not guess the kind of compiler, please report to us."
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#endif
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}
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#define mdbx_compiler_barrier() \
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mdbx_barrier(MDBX_BARRIER_COMPILER)
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#define mdbx_memory_barrier() \
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mdbx_barrier(MDBX_BARRIER_MEMORY)
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#define mdbx_coherent_barrier() \
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mdbx_barrier(MDB_CACHE_IS_COHERENT ? MDBX_BARRIER_COMPILER : MDBX_BARRIER_MEMORY)
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static MDBX_INLINE void mdb_invalidate_cache(void *addr, int nbytes) {
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mdbx_coherent_barrier();
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#if defined(__mips) && defined(__linux)
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/* MIPS has cache coherency issues.
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* Note: for any nbytes >= on-chip cache size, entire is flushed. */
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cacheflush(addr, nbytes, DCACHE);
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#elif defined(_M_MRX000) || defined(_MIPS_)
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# error "Sorry, cacheflush() for MIPS not implemented"
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#else
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/* LY: assume no mmap/dcache issues. */
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(void) addr;
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(void) nbytes;
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#endif
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}
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