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mdbx: clarify/rework invalidate_mmap_noncoherent_cache() for MIPS.
Change-Id: I70c279c2ba67191c7cb93cd8875082eb9c8e58b7
This commit is contained in:
37
src/osal.h
37
src/osal.h
@@ -407,28 +407,41 @@ static __inline void mdbx_memory_barrier(void) {
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#define mdbx_coherent_barrier() mdbx_memory_barrier()
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#endif
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#if defined(__mips) || defined(__mips__) || defined(__mips64) || \
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defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
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/* Only MIPS has explicit cache control */
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#if __has_include(<sys/cachectl.h>)
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#include <sys/cachectl.h>
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#elif defined(__mips) || defined(__mips__) || defined(__mips64) || \
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defined(__mips64__) || defined(_M_MRX000) || defined(_MIPS_) || \
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defined(__MWERKS__) || defined(__sgi)
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/* MIPS should have explicit cache control */
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#include <sys/cachectl.h>
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#endif
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static __inline void mdbx_invalidate_cache(void *addr, size_t nbytes) {
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mdbx_coherent_barrier();
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#ifndef MDBX_CPU_CACHE_MMAP_NONCOHERENT
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#if defined(__mips) || defined(__mips__) || defined(__mips64) || \
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defined(__mips64) || defined(_M_MRX000) || defined(_MIPS_)
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#if defined(DCACHE)
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defined(__mips64__) || defined(_M_MRX000) || defined(_MIPS_) || \
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defined(__MWERKS__) || defined(__sgi)
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/* MIPS has cache coherency issues. */
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#define MDBX_CPU_CACHE_MMAP_NONCOHERENT 1
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#else
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/* LY: assume no relevant mmap/dcache issues. */
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#define MDBX_CPU_CACHE_MMAP_NONCOHERENT 0
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#endif
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#endif /* ndef MDBX_CPU_CACHE_MMAP_NONCOHERENT */
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static __inline void mdbx_invalidate_mmap_noncoherent_cache(void *addr,
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size_t nbytes) {
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#if MDBX_CPU_CACHE_MMAP_NONCOHERENT
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#ifdef DCACHE
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/* MIPS has cache coherency issues.
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* Note: for any nbytes >= on-chip cache size, entire is flushed. */
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cacheflush(addr, nbytes, DCACHE);
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#else
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#error "Sorry, cacheflush() for MIPS not implemented"
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#endif /* __mips__ */
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#else
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/* LY: assume no relevant mmap/dcache issues. */
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#error "Oops, cacheflush() not available"
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#endif /* DCACHE */
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#else /* MDBX_CPU_CACHE_MMAP_NONCOHERENT */
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(void)addr;
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(void)nbytes;
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#endif
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#endif /* MDBX_CPU_CACHE_MMAP_NONCOHERENT */
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}
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/*----------------------------------------------------------------------------*/
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